In the past, integrated circuit manufacturers have customarily used one test station for individually and sequentially probe testing each die or several dice at a time on a silicon wafer for certain of its electrical characteristics. This probe operation is carried out in order to ascertain, among other things, the percentage of chips on a wafer which operate properly. Then, the probe tested wafer was transferred to an assembly packaging area where either the entire wafer or chips diced from the wafer were packaged in preparation for a subsequent burn-in operation prior to shipment to the customer.
In another, second type of wafer scale test and burn-in procedure used, for example, by the Anamartic Company of the United Kingdom where it was desired to ship an entire silicon wafer to certain customers, wafer test and burn-in procedures utilized dedicated spiral metal test patterns formed on the surface of the entire silicon wafer. These metal patterns were photodefined with a carefully controlled geometry in order to provide electrical access to the individual chips within the wafer for purposes of both probe testing the chips for their electrical characteristics and for burning-in the chips prior to shipment of the silicon wafer to the customer for use in extended memory applications and the like. Using this latter approach, the probe test and burn-in operations are accomplished by making sequential electrical connections to a dedicated spiral metal pattern for each of the probe and burn-in steps.
There is yet another, third prior art approach to wafer scale burn-in and probe testing which has been used by Lincoln Labs and Digital Equipment Company (DEC) and which does not sacrifice valuable silicon surface area for accommodating the dedicated metallization patterns as in the case of the Anamartic approach. This third method builds up dedicated probe contact areas on top of the final layer in the integrated circuit chip processing utilizing known types of metal forming and photolithographic masking and etching techniques in order to form probe and burn-in contact areas on the integrated circuit upper surface. These latter contact areas may then be connected to test and burn-in probes for carrying out the usual and required test and burn-in procedures well known in the art. The above DEC approach has been briefly described in an article by Stan Baker entitled "DEC Goes Own Way With Packaging Technology", Electronic Engineering Times, Oct. 2, 1989, incorporated herein by reference.
The first of the above three prior art probe and burn-in procedures had the obvious disadvantage of requiring that separate electrical connections be made to each die or several dice or chips on the wafer for both the probe and burn-in procedures. This requirement contributes significantly to manufacturing costs and sometimes diminishes device yields because of the significant amount of wafer handling required for the large number of individual test and burn-in operations characteristic of this procedure.
Using the second of the above three prior art approaches, namely the Anamartic wafer scale and test and burn-in procedure, this procedure had the disadvantage of requiring valuable unusable dedicated silicon wafer area to support and define the dedicated spiral metallization test patterns on the surface of the integrated circuit. In addition, if the chip yield levels for a certain wafer scale application fell below a required threshold level, the entire wafer had to be destroyed. Furthermore, during probe and burn-in, the spiral patterns of metal on the silicon wafer had to be traversed by probe from the center of the wafer to the peripheral chips thereon, and this operation is very time consuming during the probe testing phase of the process.
Using the above described third prior art approach to wafer scale testing used by Lincoln Labs and Digital Equipment Company, the requirement for further building up the integrated circuits and outer insulating and dedicated test metal probe areas as part of an add-on processes in the wafer manufacturing process operated to further reduce device yields and increase wafer processing costs. As will be seen below, this procedure as well as the other two previously described prior art methods are in significant contrast to the present invention which operates to probe and burn-in the silicon wafer only after the integrated circuit manufacture is complete and without requiring these dedicated metal test areas at the final stage of the IC manufacturing process.